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Intel® PXA255 Processor Developer’s Manual
Contents
6-14
Flash Memory Reset Using State Machine .............................................................................6-42
6-15
Flash Memory Reset Logic if Watchdog Reset is Not Necessary ...........................................6-42
6-16
MSC0/1/2.................................................................................................................................6-45
6-17
32-Bit Burst-of-Eight ROM or Flash Read Timing Diagram (MSC0[RDF] = 4,
MSC0[RDN] = 1, MSC0[RRR] = 1)..........................................................................................6-49
6-18
Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash
(MSC0[RDF] = 4, MSC0[RDN] = 1, MSC0[RRR] = 0) .............................................................6-50
6-19
32-Bit Non-burst ROM, SRAM, or Flash Read Timing Diagram - Four Data
Beats (MSC0[RDF] = 4, MSC0[RRR] = 1)...............................................................................6-51
6-20
32-Bit SRAM Write Timing Diagram (4-beat Burst (MSC0[RDN] = 2,
MSC0[RRR] = 1)......................................................................................................................6-52
6-21
32-Bit Variable Latency I/O Read Timing (Burst-of-Four, One Wait Cycle Per
Beat) (MSC0[RDF] = 2, MSC0[RDN] = 2, MSC0[RRR] = 1) ...................................................6-54
6-22
32-Bit Variable Latency I/O Write Timing (Burst-of-Four, Variable Wait Cycles
Per Beat) .................................................................................................................................6-55
6-23
Asynchronous 32-Bit Flash Write Timing Diagram (2 Writes) .................................................6-57
6-24
MCMEM1.................................................................................................................................6-58
6-25
MCATT1 ..................................................................................................................................6-58
6-26
16-Bit PC Card Memory Map ..................................................................................................6-62
6-27
Expansion Card External Logic for a One-Socket Configuration.............................................6-65
6-28
Expansion Card External Logic for a Two-Socket Configuration.............................................6-66
6-29
16-Bit PC Card Memory or I/O 16-Bit (Half-word) Access.......................................................6-67
6-30
16-Bit PC Card I/O 16-Bit Access to 8-Bit Device ...................................................................6-68
6-31
Alternate Bus Master Mode .....................................................................................................6-69
6-32
Variable Latency IO .................................................................................................................6-69
6-33
Asynchronous Boot Time Configurations and Register Defaults.............................................6-74
6-34
SMROM Boot Time Configurations and Register Defaults......................................................6-75
6-35
SMROM Boot Time Configurations and Register Defaults......................................................6-76
7-1
LCD Controller Block Diagram ..................................................................................................7-3
7-2
Temporal Dithering Concept - Single Color ...............................................................................7-6
7-3
Compare Range for TMED ........................................................................................................7-7
7-4
TMED Block Diagram ...............................................................................................................7-8
7-5
Palette Buffer Format ..............................................................................................................7-11
7-6
1 Bit Per Pixel Data Memory Organization ..............................................................................7-11
7-7
2 Bits Per Pixel Data Memory Organization ............................................................................7-12
7-8
4 Bits Per Pixel Data Memory Organization ............................................................................7-12
7-9
8 Bits Per Pixel Data Memory Organization ............................................................................7-12
7-10
16 Bits Per Pixel Data Memory Organization - Passive Mode ................................................7-13
7-11
16 Bits Per Pixel Data Memory Organization - Active Mode ...................................................7-13
7-12
Passive Mode Start-of-Frame Timing ......................................................................................7-15
7-13
Passive Mode End-of-Frame Timing .......................................................................................7-15
7-14
Passive Mode Pixel Clock and Data Pin Timing......................................................................7-16
7-15
Active Mode Timing .................................................................................................................7-16
7-16
Active Mode Pixel Clock and Data Pin Timing ........................................................................7-17
7-17
Frame Buffer/Palette Output to LCD Data Pins in Active Mode ..............................................7-20
7-18
LCD Data-Pin Pixel Ordering...................................................................................................7-22
8-1
Texas Instruments’ Synchronous Serial Frame* Format ...........................................................8-4
8-2
Motorola SPI* Frame Format.....................................................................................................8-5
8-3
National Microwire* Frame Format............................................................................................8-6
8-4
Motorola SPI* Frame Formats for SPO and SPH Programming .............................................8-13
9-1
I
2
C Bus Configuration Example .................................................................................................9-2
