Intel PXA255 - Manual (Page 34)

2-4 Intel® PXA255 Processor Developer’s Manual
System Architecture
2.2.5 Coprocessor 15 Register 1 - P-Bit
Bit 1 of this register is defined as the Page Table Memory Attribute bit or P-bit. It is not
implemented in the processor and must be written as zero. Similarly, the P-bit in the page table
descriptor in the MMU is not implemented and must be written to zero.
Table 2-2. ID Bit Definitions
CP15 Register 0 ID CP15
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Im
plem
en
tatio
n
T
radem
ar
k
Arc
h
it
e
c
tu
re
Ve
rs
io
n
Co
re
gen
er
a
tion
Co
re
Re
v
is
io
n
P
roduct
N
u
m
ber
P
roduct
Re
v
is
io
n
Reset 0 1 1 0 1 0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0
[31:24]
Implementation
Trademark
Implementation trademark.
0x69 – Intel® Corporation.
[23:16]
Architecture
Version
ARM* Architecture version of the core.
0x05 – ARM* Architecture version 5TE
[15:13] Core Generation
This field is updated when new sets of features are added to the core. This
allows software that is dependant on core features to target a specific core.
Core generation:
0b001 – Intel® XScale™ core
[12:10] Core Revision
This field is updated each time a core is revised. Differences may include
errata, software workarounds, etc.
Core revision:
0b000 – First version of the core.
0b010 – Third version of the core.
0b011 – Fourth version of the core.
[9:4] Product Number
Product Number
0b010000 – PXA255 processor
[3:0] Product Revision
This field tracks the different steppings for each ASSP.
Product Revision
0b0110 – A0 Stepping
Table 2-3. PXA255 Processor ID Values
Stepping ARM ID JTAG ID
A0 0x6905_2D06 0x6926_4013