Intel PXA255 - Manual (Page 29)

Intel® PXA255 Processor Developer’s Manual 1-5
Introduction
1.2.13.4 Hardware UART (HWUART)
The PXA255 processor has a UART with hardware flow control. The HWUART provides a partial
set of modem control pins: nCTS and nRTS. These modem control pins provide full hardware flow
control. Other modem control pins can be implemented via GPIOs. The HWUART baud rate is
programmable up to 921.6 Kbps.
The HWUART’s pins are multiplexed with the PCMCIA control pins. Because of this, these
HWUART pins operate at the same voltage as the memory bus. Also, since the PCMCIA pin
nPWE is used for variable-latency input/output (VLIO), while using these pins for the HWUART,
VLIO is unavailable. The HWUART pins are also available over the BTUART pins. When
operating over the BTUART pins, the HWUART pins operate at the I/O voltage.
1.2.14 Real-Time Clock (RTC)
The Real-Time Clock can be clocked from either crystal. A system with a 32.768-KHz crystal
consumes less power during Sleep versus a system using only the 3.6864-MHz crystal. This crystal
can be removed to save system cost. The RTC provides a constant frequency output with a
programmable alarm register. This alarm register can be used to wake up the processor from Sleep
mode.
1.2.15 OS Timers
The OS Timers can be used to provide a 3.68-MHz reference counter with four match registers.
These registers can be configured to cause interrupts when equal to the reference counter. One
match register can be used to cause a watchdog reset.
1.2.16 Pulse-Width Modulator (PWM)
The PWM has two independent outputs that can be programmed to drive two GPIOs. The
frequency and duty cycle are independently programmable. For example, one GPIO can control
LCD contrast and the other LCD brightness.
1.2.17 Interrupt Control
The Interrupt Controller directs the processor interrupts into the core’s IRQ and FIQ inputs. The
Mask Register enables or disables individual interrupt sources.
1.2.18 Network Synchronous Serial Protocol Port
The PXA255 processor has an SSP port optimized for connection to other network ASICs. This
NSSP adds a Hi-Z function to TXD, the ability to control when Hi-Z occurs, and swapping the
TXD/RXD pins.
This port is not multiplexed with other interfaces.