Intel PXA255 - Manual (Page 432)

12-32 Intel® PXA255 Processor Developer’s Manual
USB Device Controller
When DMA is used to load the transmit buffers, the interrupt generated by UDCCSx[TPC] can be
masked to allow data to be transmitted without core intervention.
12.6.6.3 Flush Tx FIFO (FTF)
The Flush Tx FIFO bit triggers a reset for the endpoint's transmit FIFO. The Flush Tx FIFO bit is
set when software writes a 1 to it or when the host performs a SET_CONFIGURATION or
SET_INTERFACE. The bit’s read value is zero.
12.6.6.4 Transmit Underrun (TUR)
The transmit underrun bit is be set if the transmit FIFO experiences an underrun. When the UDC
experiences an underrun, UDCCSx[TUR] generates an interrupt. UDCCSx[TUR] is cleared by
writing a 1 to it.
12.6.6.5 Bits 6:4 Reserved
Bits 6:4 are reserved for future use.
12.6.6.6 Transmit Short Packet (TSP)
Software uses the transmit short packet to indicate that the last byte of a data transfer has been sent
to the FIFO. This indicates to the UDC that a short packet or zero-sized packet is ready to transmit.
Software must not set this bit if a packet of 256 bytes is to be transmitted. When the data packet is
successfully transmitted, this bit is cleared by the UDC.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
12.6.7 UDC Endpoint x Control/Status Register (UDCCS4/9/14)
UDCCS4/9/14, shown in Table 12-18 , contains six bits that are used to operate endpoint(x), an
Isochronous OUT endpoint.