Artesyn ATCA-9405 Installation and Use (May 2014) - Manual (Page 81)

Service Processor
ATCA-9405 Installation and Use (6806800M71G) 81
Two SGMII and one PCIe interface are needed for ATCA-9405. The corresponding SerDes
configuration is listed in the table below. The SerDes reference clock for this configuration must
be 100 MHz.
4.8 PCI Express Interface
The P2020 supports three PCIe interfaces that are compliant with the PCIe Base Specification
Revision 1.0a. They are configued at boot time to act as either root complex or endpoint. The
PHY of the PCIe interface operates at a transmission rate of 2.5 Gbps (data rate of 2 Gbps) per
lane. The ports can be configured for x1, x2, or x4 link widths.
On ATCA-9405, PCIe Port 1 (SerDes Lane 0) is configured to x1 link width and is connected to
the PLX PEX8608 switch. P2020 acts as root complex and is responsible for blade control and
monitoring as well as PCIe hot plug handling. The remaining two PCIe Ports are not used.
For more details regarding PCIe infrastructure and hot plug handling, refer to Service
Infrastructure on page 101 .
Table 4-7 P2020 SerDes Configuration
Reset Configuration Value SerDes Configuration
cfg_IO_ports[0:3] 1110 SerDes Lane 0: PCI Express 1 (x1, 2.5 Gbps)
SerDes Lane 1: PCI Express 2 (x1, 2.5 Gbps) - not used
SerDes Lane 2: SGMII eTSEC2 (x1, 1.25 Gbps)
SerDes Lane 3: SGMII eTSEC3 (x1, 1.25 Gbps)
cfg_sgmii2 0 eTSEC2 operates in SGMII mode
cfg_sgmii3 0 eTSEC3 operates in SGMII mode
SerDes Lane 1 is not used on ATCA-9405, so it is left unconnected.