Artesyn ATCA-9405 Installation and Use (May 2014) - Manual (Page 145)

Intelligent Peripheral Management Controller
ATCA-9405 Installation and Use (6806800M71G) 145
The IPMC automatically switches the boot banks on SP, provided the failsafe logic is enabled via
OEM command.
When the fail safe logic is triggered as a result of the BMC Watchdog timeout, a System
Firmware Progress sensor SEL event is logged as follows:
Event Data Byte 1: 0xA1 (System Firmware Hang)
Event Data Byte 2: 0x00 (SPP CPU)
Event Data Byte 3: 0xXX (Failed Boot Bank ID: 0=Bank A; 1=Bank B)
Fail Safe logic makes three attempts to boot the payload successfully. After three attempts, the
fail safe logic is automatically disabled and the boot bank is left in the original state (before the
payload was booted). In addition, this logic is only enabled upon a hard reset of the IPMC
firmware, a cold or warm IPMC reset does not enable this functionality.
Fail Safe is disabled by default and can be enabled with the IPMI command Set Feature
Configuration
. For more information, see Set Feature Configuration Command on page 151 .
8.15 Payload Interface
The IPMC communicates with the payload via its host Keyboard Style Controller (KCS)
interface. The Renesas H8S provides support for LPC/KCS in hardware. KCS is defined by the
IPMI 1.5 Specification.
8.16 Payload Boot Bank Selection
The ATCA-9405 provides redundant payload boot flashes for crisis recovery. The IPMC
manages from which boot bank the payload should boot from.