Artesyn ATCA-9405 Installation and Use (May 2014) - Manual (Page 80)

Service Processor
ATCA-9405 Installation and Use (6806800M71G) 80
4.6 Local Bus
The P2020 includes an Enhanced Local Bus Controller (eLBC). The main component of the eLBC
is its memory controller, which provides a seamless 16-bit interface to many types of memory
devices and peripherals. The memory controller is responsible for controlling eight memory
banks (chip selects) shared by a general-purpose chip select machine (GPCM), an FCM, and up
to three UPM machines. The eLBC offers a multiplexed 16-bit address and data bus operating
at up to 83 MHz. Data checking and protection features, such as parity support and write
protection are included.
The eLBC supports ratios of 4, 8, and 16 between the faster internal CCB clock and slower
external bus clock. The selected divider for ATCA-9405 is 16, resulting in a local bus frequency
of 31 MHz at a platform frequency of 500 MHz (1000 MHz processor).
The eLBC provides one GPCM, one FCM, and three UPMs for the local bus to allow the
implementation of memory systems with very specific timing requirements. The GPCM
provides interfacing for simpler, lower-performance memories, and memory-mapped devices.
It has inherently lower performance because it does not support bursting. For this reason,
GPCM-controlled banks are used primarily for boot-loading from NVRAM or NOR Flash, and
access to low-performance memory-mapped peripherals.
On ATCA-9405, the GPCM provides the local bus interface to the FPGA. The FCM and UPM
controllers are not used. The FPGA is connected to chip select LCS3# and configured as 8-bit
device.
Contact sales/marketing team, if you require a detailed CPLD and FPGA specification.
4.7 SerDes Configuration
The P2020 provides four SerDes blocks that support the SGMII, serial RapidIO, and PCIe high-
speed I/O interface standards. Each SerDes can be mapped to one of the different IO interfaces
depending on power-on reset (POR) configuration.