Artesyn ATCA-9405 Installation and Use (May 2014) - Manual (Page 60)

Packet Processor
ATCA-9405 Installation and Use (6806800M71G) 60
3.2 CN6880 Processor
ATCA-9405 design is based on Cavium OCTEON II CN6880 Multi-Core MIPS64 Processors. The
CN68XX family is targeted for high-performance, high-throughput, service-rich applications in
secure datacenter, mobile internet, and borderless enterprise applications.
The CN68XX family includes six software and pin-compatible processors, with 16 to 32
cnMIPS64 v2 cores, over 85 application acceleration engines, and real time Power Optimizer
features.
High-bandwidth connectivity based on the latest standards-based SERDES I/Os including PCIe
Gen2, XAUI, DXAUI, RXAUI, SGMII, and Interlaken enables throughputs up to 40 Gbps using a
single chip or scaling to over 100 Gbps using multiple chips.
Using up to four DDR3 controllers, a 4 MB L2 Cache, and complete application acceleration,
including packet processing, Encryption/Decryption, Deep Packet Inspection (RegEx),
Compression/decompression, De-duplication, RAID, and Multi-core scaling, the CN68XX
offers both the highest compute as well as the highest throughput processing and services.
Note that the 1.5 GHz version of the processor may not be used on ATCA-9405 because of
thermal and electrical limitations. Tradeoff with regard to core count and memory size is
needed to enable usage of 1.5 GHz processor.
3.3 Cache
The CN6880 includes 37 KB of L1 instruction cache and 32 KB of L1 data cache with parity
protection and single-bit error correction for each core. The L1 caches are part of the processor
core and run at full core clock frequency. Additionally, 4 MB L2 cache is shared between all
processor cores. The L2 cache is 16-way set-associative with a 128 byte cache block, write-back
and SECDED ECC support for both the on-chip data and tags.
The functions specified in the following sections are applicable for both the Packet Processor
Units.