Artesyn ATCA-9405 Installation and Use (May 2014) - Manual (Page 132)

Intelligent Peripheral Management Controller
ATCA-9405 Installation and Use (6806800M71G) 132
8.6 POST
POST is executed at IPMC startup when either a hard (blade physically extracted/reinserted) or
cold (IPMI Command) reset is performed. POST verifies the functionality of SRAM, IPMB-0,
EEPROM data storage, FRU-Information, and all devices (primarily sensors) attached to the
IPMCs private master-only I2C bus. A detailed description of POST tests are as follows:
 FRU-Information - This test verifies that the FRU-Information is readable from the external
EEPROM where it is stored. Once read, each section's checksum is computed and
validated.
 IPMB-0 - This test reads the ready signals coming from the I2C buffers. This test passes as
long as both ready signals are active and both IPMB busses (IPMB-A and IPMB-B) are
enabled.
 EEPROM - This test verifies that the EEPROM contents are readable via I2C. Since the IPMC
stores its runtime and persistent data here, proper operation is crucial.
 Master-Only I2C - This test verifies that all expected devices attached to the master-only
I2C bus are accessible.
The IPMC contains a sensor of type 0x28 (Management Subsystem Health) which reports the
results of the IPMCs POST. If all tests pass, then the sensor reads Performance Met; otherwise
it reports Performance Lags. If POST fails, the POST sensor generates an event to the SEL with
the Performance Met/Performance Lag offsets.
To obtain results of POST, the IPMC supports the IPMI standard command Get Self Test
Results
with OEM extensions. This IPMI command can be run at anytime.
Int ADC MMC RTM 12V
3.3V
1.8V
0.9V ATMEL ADC
0x94 MMC Mezzanine
Card Temperature LM75
Table 8-4 Voltage and Temperature Sensor Devices (continued)
I2C address I2C bus Domain Purpose Device