Artesyn ATCA-9405 Installation and Use (May 2014) - Manual (Page 65)

Packet Processor
ATCA-9405 Installation and Use (6806800M71G) 65
3.7 PCI Express Interface
CN6880 integrates two PCIe Interfaces that are compliant with the PCIe Base Specification
Revision 2.0. They are configured at boot time to act as either root complex or endpoint. The
PHY of the PCIe interface supports transmission rate of up to 5.0 Gbps per lane. The two
interfaces can be configured as one single or two independent ports with x1, x2, x4, or x8 link
widths.
On ATCA-9405, PCIe Interface 0 (using QLM3 SerDes module) is configured to x1 link width and
is connected to the PLX PEX8608 switch. For more details regarding PCIe infrastructure, refer
to
Service Infrastructure on page 101 .
PCIe Interface 1 is not used on ATCA-9405.
3.8 Ethernet Interface
The CN6880 provides a number of integrated on-chip Ethernet controllers and supports
various interfaces standards. The CN6880 family can implement up to:
 16 SGMII/1000BASE-X SerDes interfaces through up to 4 four-port (four-lane) packet
interfaces. A full-duplex port consists of four external pins, a differential output pair and a
differential input pair. CN6880 couples logic that implements the SGMII and/or 1000BASE-
X protocols on SerDes lanes with a 10/100/1000 802.3 MAC.
 Five XAUI SerDes interfaces in up to 4 four-lane packet interfaces. Each interface consists
of 16 external pins in total, four differential output pairs plus four differential input pairs.
CN6880 couples logic that implements the XAUI, reduced XAUI (RXAUI) or double data
rate XAUI (DXAUI) interface/protocols on SerDes lanes with an IEEE 802.3-2005 MAC.
QLM3 PCI-Express XAUI, SGMII PCI Express Gen 1
100 MHz
QLM4 PCI Express XAUI, DXAUI, SGMII DXAUI
156.25 MHz
Table 3-4 CN6880 SerDes Configuration (Interlaken Mode) (continued)
QLM Supported Interfaces Configuration