Artesyn ATCA-9405 Installation and Use (May 2014) - Manual (Page 72)

Service Processor
ATCA-9405 Installation and Use (6806800M71G) 72
4.2 P2020 Processor
A Freescale P2020 QorIQ Communication Processor is used on ATCA-9405 as the onboard SP.
The processor is manufactured in 45nm process technology and combines dual Power
Architecture™ e500v2 processor cores with system logic required for networking, wireless
infrastructure, and telecommunications applications.
The P2020 is available with three speed grades running at 800 MHz, 1000 MHz, and 1200 MHz
core clock frequency. All speed grades are supported, the default speed grade on ATCA-9405
is 1.0GHz. Additionally, the board is prepared to support all three speed grades of P2010 single
core derivative.
4.3 Cache
The P2020 includes 32 KB of L1 instruction cache and 32 KB of L1 data cache with parity
protection for each core. L1 caches can be locked entirely or on a per-line basis, with separate
locking for instructions and data. The 512 KB L2 cache is common to both processors and has
full ECC protection on 64-bit boundary and supports instruction caching, data caching, or both
modes. The L1 and L2 caches are part of the P2020 core complex and run at full core clock
frequency.
4.4 Main Memory
4.4.1 Memory Interface
The P2020 memory controller on ATCA-9405 is configured for DDR3 SDRAM mode. The
controller provides a 72-bit (64-bit data plus 8-bit for ECC) wide DDR3 interface (channel) that
connects the P2020 with a single DDR3 DIMM socket.
Two physical memory banks (chip select signals) are implemented on DIMM socket to allow
use of single-rank and dual-rank DIMM modules.