17 ipmc e-keying status register, Table 6-70, Ipmc e-keying status register – Artesyn ATCA-7365-CE Installation and Use (May 2014) User Manual
Page 209: Maps and registers
Maps and Registers
ATCA-7365-CE Installation and Use (6806800L73J)
209
6.4.17 IPMC E-Keying Status Register
6
Control output Signal UC4_EQ_RX:
0: UC4_EQ_RX is driven low.
1: UC4_EQ_RX is tri-state.
0
LPC: r/w
IPMC: r
7
Control output Signal UC4_EQ_TX:
0: UC4_EQ_TX is driven low.
1: UC4_EQ_TX is tri-state.
0
LPC: r/w
IPMC: r
Table 6-69 Update Channel Equalization Control Register (continued)
Address Offset: 0x48
Bit
Description
Default
Access
Table 6-70 IPMC E-Keying Status Register
Address Offset: 0x49
Bit
Description
Default
Access
4:0
IPMC_UPDCH_[4:0]. IPMC electronic key signals
Ext.
LPC: r
5
IPMC_FAB1_10G_SEL_.
Ext.
LPC: r
6
IPMC_FAB2_10G_SEL_.
Ext.
LPC: r
7
Reserved
0
r