Artesyn ATCA-7365-CE Installation and Use (May 2014) - Manual (Page 198)

Maps and Registers
ATCA-7365-CE Installation and Use (6806800L73J) 198
6.4.10.8 IPMC Reset Source Register
The IPMC Reset Source Register stores the source of the most recent reset. A one in the register
bit indicates that the associated reset has occurred. If more than one reset occurs from
different sources without clearing the corresponding register bits, one can not determine the
most recent reset source since more than one bit will be set. The same situation will happen, if
two reset sources go active at the same time.
Table 6-55 IPMC Reset Source Register
Address Offset: 0x17
Bit Description Default Access
0 PWR_GOOD Payload Power-on reset
1: Reset occurred PWR_GOOD:1 IPMC: r/w1c
1 XDP0_BRD_PWROK CPU Debugger System reset request
1: Reset occurred PWR_GOOD:0 IPMC: r/w1c
2 PB_RST_ face plate push button reset
1: Reset occurred PWR_GOOD:0 IPMC: r/w1c
3 XDP1_DBRST_ CPU Debugger reset
1: Reset occurred PWR_GOOD:0 IPMC: r/w1c
4 RTM_PB_RST_ Reset key at RTM
1: Reset occurred PWR_GOOD:0 IPMC: r/w1c
5 CPU_RST_ CPU Reset signal from CPU
1: Reset occurred PWR_GOOD:0 IPMC: r/w1c
6 XDP0_DBRST_ CPU Debugger reset
1: Reset occurred PWR_GOOD:0 IPMC: r/w1c
7 IPMC_RST_ REQ_ Payload Reset from IPMC.
1: Reset occurred PWR_GOOD:0 IPMC: r/w1c