Artesyn ATCA-7365-CE Installation and Use (May 2014) - Manual (Page 186)

Maps and Registers
ATCA-7365-CE Installation and Use (6806800L73J) 186
6.4.2 IPMC SPI Register Map
The FPGA registers may be accessed via IPMC SPI transactions (with the signal
IPMC_SPI_SS_FPGA_ asserted). A SPI write access to an address not listed in this table or not
marked with an “X” in the IPMC SPI column is ignored. A corresponding read access delivers
always zero.
Table 6-40 FPGA Register Map Overview
Address
Offset
1 LPC I/O
IPMC
SPI
Description
0x00 x x Module Identification Register
0x01 x x FPGA Version Register
0x03 - 0x05 x x Serial Line Routing Registers
0x06 x x IPMC Power Level Register
0x08 x x SPD PROM MUX Control Register
0x10 x x BIOS Reset Source Register
0x11 x x Reset Mask Register
0x12 x x BIOS IPMC Watch dog timeout Register
0x13 x - BIOS Push Button Enable Register
0x14 x x OS Reset Source Register
0x15 x x OS IPMC Watch dog timeout Register
0x16 - x IPMC Watch dog timeout Register
0x17 - x IPMC Reset Source Register
0x18 -0x19 x - RTM SPI Interface
0x20 x - External Interrupt Status Register
0x21 x x Processor Hot Status/Control Register
0x22 x - Telecom Status/Control Register
0x23 – 0x2D x - Interrupt Mask and Map Registers
0x40 x - Flash Control and Status Register
0x41 – 0x42 x - Boot Flash Write Enable Registers
0x43 x x BIOS Boot Mode Register