Artesyn ATCA-7365-CE Installation and Use (May 2014) - Manual (Page 197)

Maps and Registers
ATCA-7365-CE Installation and Use (6806800L73J) 197
6.4.10.7 IPMC Watchdog Timeout Register
The IPMC SW set the corresponding bit to signal an IPMC watchdog timeout event. When the
IPMC Watchdog Timeout bit is set from low to high, the corresponding bits in
Table 6-50 BIOS
IPMC Watchdog Timeout Register and Table 6-53 OS IPMC Watchdog Timeout Register are set.
IPMC needs to clear the IPMC watchdog timeout bit to arm IPMC watchdog timeout event
recognition.
Table 6-54 IPMC Watchdog Timeout Register
Address Offset: 0x16
Bit Description Default Access
0 IPMC Watchdog Timeout:
0: No IPMC Watchdog Timeout
1: IPMC Watchdog Timeout occurred PWR_GOOD:0 IPMC: r/w
1 IPMC Pre-Timeout
0: No IPMC Pre-Timeout
1: IPMC Pre-Timeout occurred PWR_GOOD:0 IPMC: r/w
7:2 Reserved 0 r