Artesyn ATCA-7365-CE Installation and Use (May 2014) - Manual (Page 201)

Maps and Registers
ATCA-7365-CE Installation and Use (6806800L73J) 201
6.4.12.3 Processor Hot Status/Control Register
5 THERM_ALERT_ IRQ request from IOH Thermo-sensor Ext. LPC: r
6 APB_ALARM An 48V input alarm (low voltage, etc) Ext. LPC: r
7 RTM_SPI_MISO RTM interrupt sources
0: RTM_SPI_MISO is high. No RTM interrupt.
1: RTM_SPI_MISO is low. One or more RTM
interrupt sources are active. When RTM SPI
Master face is active the current level is
latched. Ext. LPC: r
1. When an interrupt is active the corresponding status bit is read 1.
Table 6-59 External Interrupt Status Register (continued)
Address Offset: 0x20
Bit Signal 1 Description Default Access
Table 6-60 Processor Hot Status/Control Register
Address Offset: 0x21
Bit Signal Description Default Access
0 CPU0_PRCHT_ IPMC signals interrupt Ext. LPC: r
1 CPU1_PRCHT_ Interrupt input from payload Temp sensor Ext. LPC: r
2 CPU0_PRCHT_ Interrupt from SFMEM Module 0 LPC: r/w
3 CPU1_PRCHT_ IRQ request from 82599 Thermsen0 0 LPC: r/w
7:4 - Reserved - r