Artesyn ATCA-7365-CE Installation and Use (May 2014) - Manual (Page 208)

Maps and Registers
ATCA-7365-CE Installation and Use (6806800L73J) 208
6.4.16 Update Channel Equalization Control Register
7:4 Reserved 0 r
Table 6-68 SFMEM Module Configuration Register (continued)
Address Offset: 0x45
Bit Description Default Access
Table 6-69 Update Channel Equalization Control Register
Address Offset: 0x48
Bit Description Default Access
0 Control output Signal UC1_EQ_RX:
0: UC1_EQ_RX is driven low.
1: UC1_EQ_RX is tri-state. 0 LPC: r/w
IPMC: r
1 Control output Signal UC1_EQ_TX:
0: UC1_EQ_TX is driven low.
1: UC1_EQ_TX is tri-state. 0 LPC: r/w
IPMC: r
2 Control output Signal UC2_EQ_RX:
0: UC2_EQ_RX is driven low.
1: UC2_EQ_RX is tri-state. 0 LPC: r/w
IPMC: r
3 Control output Signal UC2_EQ_TX:
0: UC2_EQ_TX is driven low.
1: UC2_EQ_TX is tri-state. 0 LPC: r/w
IPMC: r
4 Control output Signal UC3_EQ_RX:
0: UC3_EQ_RX is driven low.
1: UC3_EQ_RX is tri-state. 0 LPC: r/w
IPMC: r
5
Control output Signal UC3_EQ_TX:
0: UC3_EQ_TX is driven low.
1: UC3_EQ_TX is tri-state.
0 LPC: r/w
IPMC: r