Artesyn ATCA-7365-CE Installation and Use (May 2014) - Manual (Page 128)

BIOS
ATCA-7365-CE Installation and Use (6806800L73J) 128
4.12.4.3 POST Error
If an error has occured during the BIOS phase, a POST Error event is generated. There is only one
POST Error event per boot generated.
A set bit at a Result DWORD bit position implies that the error associated with that position has
occurred. If there was a error which has no corresponding bit in the Result DWORDs, the bit 0
form the Second DWORD is set (OEM: Unspecified Error).
02h-07h Date/Time Fields BYTE These fields contain the BCD
representation of the date and time
08h-0Bh Memory Information UINT32 OEM extension
Table 4-33 Memory InformaTion Definition
Bit Description
0-7 reserved
8-15 DIMM number per Channel 0..1
16-23 DIMM channel 0..2
24-31 CPU Socket 0..1
Table 4-32 Multi-bit ECC Memory Error Event Format (continued)
Offset Name Format Description
Table 4-34 POST Error Event Format
Offset Name Format Description
00h Event Type BYTE Event Type = 02h
01h Length BYTE always 0Ch
02h-07h Date/Time Fields BYTE These fields contain the BCD
representation of the date and time
08h-0Bh Result First DWORD UINT32 See Table 4-35 on page 129
0Ch-0Fh Result Second DWORD UINT32 See Table 4-36 on page 129