Artesyn ATCA-7365-CE Installation and Use (May 2014) - Manual (Page 182)

Maps and Registers
ATCA-7365-CE Installation and Use (6806800L73J) 182
6.3.4.2.9 Modem Status Register (MSR)
This 8-bit register provides the current state of the control lines from the modem or data set
(or a peripheral device emulating a modem) to the processor. In addition to this current state
information, four bits of the Modem Status register provide change information. Bits 03:00 are
set to a logic 1 when a control input from the Modem changes state. They are reset to a logic 0
when the processor reads the Modem Status register.
When bits 0, 1, 2, or 3 are set to logic 1, a Modem Status interrupt is generated if bit 3 of the
Interrupt Enable Register is set.
7 FIFO data error
In the FIFO mode, LSR7 is set when there is at least one parity, framing, or
break error in the FIFO. It is cleared when the microprocessor reads the LSR
and there are no subsequent errors in the FIFO. If FIFO is not used, bit always
reads 0:
1: FIFO data error encountered
0: No FIFO error encountered 0 LPC: r
Table 6-35 Line Control Register (LCR) (continued)
LPC IO Address: Base + 5
Bit Description Default Access
Table 6-36 Modem Status Register (MSR)
LPC IO Address: Base + 6
Bit Description Default Access
0 Change in clear-to-send (DCTS) indicator
DCTS indicates that the CTS# input has changed state since the last time it
was read by the CPU. When DCTS is set (autoflow control is not enabled and
the modem status interrupt is enabled), a modem status interrupt is
generated. When autoflow control is enabled (DCTS is cleared), no interrupt
is generated:
1: Change in state of CTS# input since last read
0: No change in state of CTS# input since last read 0 LPC: r/w