Altera 100G Interlaken MegaCore Function - Manual (Page 95)

RXFIFO Address Width
The RXFIFO Address Width parameter specifies the number of bits in the address (offset) of an entry in
the RX Reassembly FIFO. The number of bits is log
2
of the depth of this FIFO. Each RX Reassembly FIFO
entry is a 64-bit word.
The default value for the RXFIFO Address Width parameter is 12, specifying this FIFO can hold 2
12
(==4K) 64-bit words. Adjusting this parameter may affect your ability to close timing for your design.
However, you can adjust this parameter subject to the successful closure of the timing.
Related Information
Modifying Hidden Parameter Values on page 9-3
SWAP_TX_LANES and SWAP_RX_LANES (Data Word Lane Swapping)
The 100G Interlaken IP core supports a lane reversal feature (lane swapping). Lane swapping parameters
determine the order in which blocks are distributed and gathered from the lanes. The 100G Interlaken IP
core provides the following two options for the lane order:
• Straight Lane order. The transmitter sends Interlaken blocks sequentially across the lanes starting with
the top lane, ending with Lane 0. The receiver takes in Interlaken blocks starting with the top lane,
ending with Lane 0.
Figure 9-1: Straight Lane Order
Lane N
.
.
.
Lane 2
Lane 1
Lane 0
• Swapped Lane order. The transmitter sends Interlaken blocks sequentially across the lanes starting
with Lane 0, ending with Lane N. The receiver takes in Interlaken blocks starting with Lane 0, ending
with Lane N.
9-2 RXFIFO Address Width
UG-01128
2015.05.04
Altera Corporation Advanced Parameter Settings
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