Altera 100G Interlaken MegaCore Function - Manual (Page 90)

Table 8-3: Programming the Hard PCS Registers in Arria 10 Devices
To turn on the PRBS feature in the hard PCS for IP core variations that target an Arria 10 device, you must
program the following hard PCS registers in the order shown, for each of the TX and RX sides. These registers are
not accessible using the 100G Interlaken IP core management interface. You must access these registers through
the Arria 10 transceiver reconfiguration interface of the 100G Interlaken IP core.
Ensure you set these register bits using a read-modify-write register access sequence (per register), to avoid
modifying the other register fields.
TX Register Offset Bits Meaning Action
1 0x6
[2:0] TX test enable Set this field to the value of 3'b100 to enable
the PRBS pattern generator in the
transmitter.
[3] PRBS width select Set this bit to the value of 0 to specify that
the PRBS width is 64 bits.
[7:6] Enable TX PRBS clock Set this field to the value of 2'b01 to enable
the TX PRBS clock.
2 0x7
[2] Invert TX channels Set this bit to the value of 0 to specify that
the outgoing PRBS be inverted, or set this bit
to the value of 1 to specify that the outgoing
PRBS not be inverted. The default value of
this register field is 0. By default, the
outgoing PRBS is inverted.
[5] Enable PRBS9
Set one of these bits to the value of 1, and the
others to the value of 0, to select the TX
polynomial.
[6] Enable PRBS15
[7] Enable PRBS23
3 0x8 [4] Enable PRBS31
RX Register Offset Bits Meaning Action
1 0xA
[4] Invert RX channels Set this bit to the value of 0 to specify that
the PCS should expect the incoming PRBS
to be inverted, or set this bit to the value of
1 to specify that the PCS should not expect
the incoming PRBS to be inverted. The
default value of this bit is 0. In loopback
mode, you should set this bit to match the
setting in the PRBS transmitter.
[7] Enable RX PRBS clock Set this bit to the value of 1 to enable the RX
PRBS clock.
UG-01128
2015.05.04
Setting up PRBS Mode in Arria 10 Devices 8-5
100G Interlaken IP Core Test Features Altera Corporation
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