Altera 100G Interlaken MegaCore Function User Manual
Page 104
The following figures explain the derivation of the minimum frequency requirements.
Figure A-2: Packet Processing Requirements in Single Segment Mode
64
Bytes
Idle
64 Bytes at 300 MHz
512
1
64
Bytes
1 - 64
Bytes
65 - 128 Bytes
512
2
64
Bytes
64
Bytes
129 - 192 Bytes in 10 ns
512
3
1 - 64
Bytes
A 65-byte packet comprises (65 + 20) x 8 = 680 bits. Therefore, for traffic that consists mainly of 65-byte
packets, the most inefficient traffic possible, the user interface must handle:
100 x 1,000,000,000 bits/sec ÷ 680 = 147 Million packets/sec, or one packet every 6.8 ns.
Case 2 in the single segment mode figure shows that the user interface requires two cycles to process each
65-byte packet. At 300 MHz, two cycles take 6.66 ns, which is a sufficiently small amount of time.
A 129-byte packet comprises (129 + 20) x 8 = 1192 bits. Therefore, for traffic that consists mainly of 129-
byte packets, the user interface must handle:
100 x 1,000,000,000 bits/sec ÷ 1192 = 83.9 Million packets/sec, or one packet every 11.9 ns.
Case 3 in the single segment mode figure shows that the user interface requires three cycles to process
each 129-byte packet. At 300 MHz, three cycles take 10 ns, which is a sufficiently small amount of time.
The same calculations applied to lower frequencies yield an average time per packet that is not sufficiently
short. Therefore, 300 MHz is the recommended frequency for the two user data transfer interface clocks
in your single segment mode 100G Interlaken IP core. For logistical clocking reasons, this frequency is
also recommended for your 24-lane variation in dual segment mode.
Figure A-3: Packet Processing Requirements in Dual Segment Mode
64
Bytes
64
Bytes
2
64
Bytes
33
Bytes
33
Bytes
Two 65 Byte Packets at 225 MHz
Two 129 Byte Packets in 22.23 ns
512
512
1
64
Bytes
1
Byte
32
Bytes
(next pkt)
1
Byte
32
Bytes
(next pkt)
In dual segment mode, a 65-byte packet or a 129-byte packet can be followed in the same cycle by the first
32 bytes of the following packet. The table summarizes the numbers illustrated in the figure.
A-2
Performance and Fmax Requirements for 100G Ethernet Traffic
UG-01128
2015.05.04
Altera Corporation
Performance and Fmax Requirements for 100G Ethernet Traffic