100g interlaken ip core testbench, 100g interlaken ip core testbench -1 – Altera 100G Interlaken MegaCore Function User Manual
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100G Interlaken IP Core Testbench
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2015.05.04
UG-01128
When you generate an 100G Interlaken IP core variation with Verilog HDLsynthesis and simulation
models, the software generates an example design and testbench to simulate your 100G Interlaken IP core
variation. The testbench provides system and PLL reference clocks and connects the TX output pins of the
IP core to its RX input pins, implementing physical layer loopback.
In simulation, the testbench generates packets on the IP core TX user data transfer interface. The IP core
sends these packets on the loopback Interlaken link. After the IP core receives the packets on the loopback
Interlaken link, it processes the Interlaken packets and transmits them on the RX user data transfer
interface. The testbench checks that the packets it receives on the IP core RX user data transfer interface
are consistent with the packets sent in.
Figure 7-1: 100G Interlaken IP Core Testbench Block Diagram
The TX PLL is present only in the example designs for Arria 10 variations.
PLL
Loopback
TX Lanes
RX Lanes
Example Design
Top Testbench
Packet
Generator
Control & Status
Registers
Packet
Checker
100G Interlaken
MegaCore
Function
System Clock
Generator
PLL Reference
Clock Generator
TX PLL
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