Altera 100G Interlaken MegaCore Function - Manual (Page 33)

Arria 10 Transceiver Reconfiguration Interface on page 4-3
Transceiver Reconfiguration Controller Interface
100G Interlaken IP core variations that target an Arria V or a Stratix V device require an external reconfi‐
guration controller to function correctly in hardware. 100G Interlaken IP core variations that target an
Arria 10 device include a reconfiguration controller block and do not require an external reconfiguration
controller.
Related Information
• Altera Transceiver PHY IP Core User Guide
Describes the Altera Transceiver Reconfiguration Controller and the signals that connect to the
100G Interlaken IP core transceiver reconfiguration controller interface.
Arria 10 External PLL Interface
100G Interlaken IP core variations that target an Arria 10 device require an external transceiver PLL to
function correctly in hardware. 100G Interlaken IP core variations that target an Arria V or Stratix V
device include the transceiver PLLs and do not require that you configure any additional PLLs.
Related Information
• Adding the External PLL on page 2-12
Describes how to generate an external TX PLL, including parameter requirements.
• Arria 10 External PLL Interface Signals on page 5-15
• Arria 10 Transceiver PHY User Guide
Information about the Arria 10 transceiver PLLs and clock network.
Arria 10 Transceiver Reconfiguration Interface
The Arria 10 transceiver reconfiguration interface provides access to the registers in the embedded Arria
10 Native PHY IP core. This interface provides direct access to the hard PCS registers on the device.
This interface is available only in variations that target an Arria 10 device. In variations that target an
Arria V device or a Stratix V device, user logic reconfigures the transceivers through the transceiver
reconfiguration controller, an external block that you must instantiate in your design outside the
100G Interlaken IP core.
The Arria 10 transceiver reconfiguration interface complies with the Avalon Memory-Mapped (Avalon-
MM) specification defined in the Avalon Interface Specifications.
Related Information
Avalon Interface Specifications
Defines the Avalon Memory-Mapped (Avalon-MM) specification.
Arria 10 Transceiver PHY User Guide
Information about the Arria 10 transceiver reconfiguration interface.
Arria 10 Transceiver Registers
Information about the Arria 10 transceiver registers.
UG-01128
2015.05.04
Transceiver Reconfiguration Controller Interface 4-3
Functional Description Altera Corporation
Send Feedback