Altera 100G Interlaken MegaCore Function - Manual (Page 6)

• Supports Packet mode and Interleaved (Segmented) mode for user data transfer.
• Supports dual segment mode for efficient user data transfer.
• Supports up to 256 logical channels in out-of-the-box configuration.
• Supports optional user-controlled in-band flow control with 1, 2, 4, 8, or 16 16-bit calendar pages.
• Supports optional out-of-band flow control blocks.
• Supports memory block ECC in Stratix V and Arria 10 devices.
Related Information
Interlaken Protocol Specification, Rev 1.2
IP Core Supported Combinations of Number of Lanes and Data Rate
Table 1-1: 100G Interlaken IP Core Supported Combinations of Number of Lanes and Data Rate
Yes indicates a supported combination.
Number of Lanes
Lane Rate (Gbps)
6.25 10.3125 12.5
12 — Yes Yes
24 Yes — —
IP Core Theoretical Raw Aggregate Bandwidth
Table 1-2: 100G Interlaken IP Core Theoretical Raw Aggregate Bandwidth in Gbps
Number of Lanes
Lane Rate (Gbps)
6.25 10.3125 12.5
12 — 123.75 150.00
24 150.00 — —
Device Family Support
The following table lists the device support level definitions for Altera IP cores.
Table 1-3: Altera IP Core Device Support Levels
FPGA Device Families
Preliminary support — The core is verified with preliminary timing models for this device family. The IP
core meets all functional requirements, but might still be undergoing timing analysis for the device family. It
can be used in production designs with caution.
1-2 IP Core Supported Combinations of Number of Lanes and Data Rate
UG-01128
2015.05.04
Altera Corporation About This MegaCore Function
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