About this megacore function, Features, About this megacore function -1 – Altera 100G Interlaken MegaCore Function User Manual
Page 5: Features -1
About This MegaCore Function
1
2015.05.04
UG-01128
Interlaken is a high-speed serial communication protocol for chip-to-chip packet transfers. The Altera
®
100G Interlaken MegaCore
®
function implements the Interlaken Protocol Specification, Revision 1.2 . It
supports specific combinations of number of lanes (12 or 24) and lane rates from 6.25 gigabits per second
(Gbps) to 12.5 Gbps, on Stratix
®
V, Arria
®
V GZ, and Arria 10 devices, providing raw bandwidth of
123.75 Gbps to 150 Gbps.
Interlaken provides low I/O count compared to earlier protocols, supporting scalability in both number of
lanes and lane speed. Other key features include flow control, low overhead framing, and extensive
integrity checking. The 100G Interlaken MegaCore function incorporates a physical coding sublayer
(PCS), a physical media attachment (PMA), and a media access control (MAC) block.
Figure 1-1: Typical Interlaken Application
FPGA/
ASIC
In
terlak
en
In
terlak
en
FPGA/
ASIC
In
terlak
en
In
terlak
en
FPGA/
ASIC
In
terlak
en
Up to
150 Gbps
Up to
150 Gbps
Traffic
Management
Packet
Processing
Ethernet
MAC/Framer
Switch
Fabric
To Line
Interface
Related Information
Features
The 100G Interlaken MegaCore function has the following features:
• Compliant with the Interlaken Protocol Specification, Rev 1.2.
• Supports 12 and 24 serial lanes in configurations that provide up to 150 Gbps raw bandwidth.
• Supports per-lane data rates of 6.25, 10.3125, and 12.5 Gbps using Altera on-chip high-speed
transceivers.
• Supports dynamically configurable BurstMax and BurstMin values.
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