Dual segment mode, Dual segment mode -8 – Altera 100G Interlaken MegaCore Function User Manual
Page 38
In Packet mode, the 100G Interlaken IP Core performs Optional Scheduling Enhancement based on
Section 5.3.2.1.1 of the Interlaken Protocol Specification, Revision 1.2. The IP core ignores the
itx_sob
and
itx_eob
signals. Instead, the IP core performs optional enhanced scheduling based on the settings of
BurstMax
,
BurstMin
, and
BurstShort
.
In Interleaved mode, the 100G Interlaken IP Core inserts burst control words on the Interlaken link based
on the
itx_sob
and
itx_eob
inputs. The internal optional enhanced scheduling is disabled and the
BurstMax and BurstMin values are ignored. BurstShort is still in effect. To avoid overflowing the transmit
FIFO, you should not send a burst that is longer than 1024 bytes.
In Interleaved mode or in Packet mode, the 100G Interlaken IP core is capable of accepting non-
interleaved data on the TX user data transfer interface (
itx_din_words
). However, if the IP core is in
Interleaved mode, the application must drive the
itx_sob
and
itx_eob
inputs correctly.
In Interleaved mode or in Packet mode, the 100G Interlaken IP core can generate interleaved data
transfers on the RX user data transfer interface (
irx_dout_words
). The application must be able to accept
interleaved data transfers if the Interlaken link partner transmits them on the Interlaken link. In this case,
the Interlaken link partner must send traffic in Interleaved mode that conforms with the 100G Interlaken
IP core
BurstShort
value.
Note: Altera recommends that the transmitter (link partner) only send packets with a minimum packet
size of 64 bytes.
Related Information
•
on page 3-6
•
100G Interlaken IP Core User Data Transfer Interface Signals
•
Dual Segment Mode
In dual segment mode, the 100G Interlaken IP core can minimize wasted bandwidth on the user data
transfer interface by starting a packet transfer at Byte 31 (Word 3) of the data bus
(
irx_dout_words[511:0]
), if the previous packet ended with four or fewer 64-bit words transferred in
the current
rx_usr_clk
cycle.
In dual segment mode, the IP core is capable of accepting dual segment input on the TX user data transfer
interface (
itx_din_words[511:0]
). However, the application can control IP core input signals to specify
that the current incoming data transfer does not use dual segment mode. In addition, if you tie the
relevant input signals (
itx_sob[0]
,
itx_sop[0]
, and
itx_num_valid[3:0]
) permanently low in your
design, the Quartus II Fitter compiles away the IP core logic that generates dual segment output from the
IP core.
4-8
Dual Segment Mode
UG-01128
2015.05.04
Altera Corporation
Functional Description