100g interlaken megacore function signals, 100g interlaken ip core clock interface signals, 100g interlaken megacore function signals -1 – Altera 100G Interlaken MegaCore Function User Manual
Page 59: 100g interlaken ip core clock interface signals -1
100G Interlaken MegaCore Function Signals
5
2015.05.04
UG-01128
The 100G Interlaken MegaCore function communicates with the surrounding design through multiple
external signals.
100G Interlaken IP Core Clock Interface Signals
Table 5-1: 100G Interlaken IP Core Clock Interface
Signal Name
Direction
Width
(Bits)
Description
Clock Ports
pll_ref_clk
Input
1
Transceiver reference clock for the RX transceiver
PLL in IP core variations that target an Arria 10
device. Transceiver reference clock for RX and TX
transceiver PLLs in all other variations.
Table 5-2: 100G Interlaken IP Core Supported pll_
ref_clk Frequencies
The sets of valid frequencies vary with the per-lane
data rate of the transceivers.
Per-Lane Data Rate
Valid pll_ref_clk Frequencies
(MHz)
10.3125
206.25, 257.8125, 322.265625,
412.5, 515.625, 644.53125
12.5, 6.25
156.25, 195.3125, 250, 312.5,
390.625, 500, 625
The
pll_ref_clk
input clock frequency must match
the value you specify for the Transceiver reference
clock frequency parameter.
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