Altera 100G Interlaken MegaCore Function - Manual (Page 73)

requirements to support the Arria 10 transceivers. The following 100G Interlaken IP core interfaces are
device specific:
Transceiver Reconfiguration Controller Interface Signals on page 5-15
Arria 10 External PLL Interface Signals on page 5-15
Arria 10 Transceiver Reconfiguration Interface Signals on page 5-16
Transceiver Reconfiguration Controller Interface Signals
100G Interlaken IP core variations that target an Arria V or a Stratix V device require an external reconfi‐
guration controller to function correctly in hardware. 100G Interlaken IP core variations that target an
Arria 10 device include a reconfiguration controller block and do not require an external reconfiguration
controller.
Table 5-7: 100G Interlaken IP Core Arria V and Stratix V Transceiver Reconfiguration Controller Interface
Signals
Signal Name Direction Width
(Bits)
Description
reconfig_to_xcvr
Input 70 bits
per
reconfi‐
guration
interface.
Bus from the external transceiver reconfiguration
controller to the 100G Interlaken IP core. The bus
includes signals fro multiple transceiver reconfigura‐
tion interfaces. The reconfiguration controller has one
interface to control each transceiver channel (one per
Interlaken lane) plus one interface to control each TX
PLL configured in the IP core. The width of each
reconfiguration controller output reconfiguration
interface is 70 bits.
reconfig_from_xcvr
Output 46 bits
per
reconfi‐
guration
interface
Bus to the external transceiver reconfiguration
controller from the 100G Interlaken IP core. The bus
includes signals for multiple reconfiguration
interfaces of the transceiver reconfiguration
controller. The reconfiguration controller has one
interface for each transceiver channel (one per
Interlaken lane) plus one interface for each TX PLL
configured in the IP core. The width of each reconfi‐
guration controller input reconfiguration interface is
46 bits.
Arria 10 External PLL Interface Signals
100G Interlaken IP core variations that target an Arria 10 device require an external transceiver PLL to
function correctly in hardware. 100G Interlaken IP core variations that target an Arria V or Stratix V
device include the transceiver PLLs and do not require that you configure any additional PLLs.
UG-01128
2015.05.04
Transceiver Reconfiguration Controller Interface Signals 5-15
100G Interlaken MegaCore Function Signals Altera Corporation
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