Altera 100G Interlaken MegaCore Function - Manual (Page 21)

The following simple instructions show you how to instantiate an Altera Transceiver Reconfiguration
Controller and how to connect the design blocks:
Generating the Reconfiguration Controller
You can use the IP Catalog to generate an Altera Transceiver Reconfiguration Controller.
In the Transceiver Reconfiguration Controller parameter editor, you select the features of the transceiver
that can be dynamically reconfigured. However, you must ensure that the following two features are
turned on:
1. Enable PLL calibration
2. Enable Analog controls
You must also set the value of the Number of reconfiguration interfaces parameter. Each TX PLL
requires its own reconfiguration interface, whether or not you intend to reconfigure it. The following
formula determines the correct number of reconfiguration interfaces:
NUMBER_OF_RECONFIGURATION_INTERFACES = NUMBER_OF_LANES + NUMBER_OF_TX_PLLs
where
•
NUMBER_OF_LANES
is the total number of physical lanes used in your implemented design.
•
NUMBER_OF_TX_PLLs
is the total number of transceiver blocks (number of TX PLLs) used in your
design.
For example, for a design that includes a 12-lane Interlaken variation that is configured in two transceiver
blocks, you must set Number of reconfiguration interfaces to the value of 14.
Connecting the Reconfiguration Controller to the IP Core
The Reconfiguration Controller communicates with the 100G Interlaken IP core on two busses:
•
reconfig_to_xcvr
(output)
•
reconfig_from_xcvr
(input)
Each of these busses connects to the bus of the same name in the 100G Interlaken IP core.
You must also connect the following signals:
•
mgmt_clk_clk
: Reconfiguration Controller clock (input)
•
mgmt_rst_reset
: Reconfiguration Controller reset (input)
•
reconfig_busy
: Reconfiguration Controller busy indication (output)
UG-01128
2015.05.04
Generating the Reconfiguration Controller 2-11
Getting Started With the 100G Interlaken IP Core Altera Corporation
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