Altera 100G Interlaken MegaCore Function - Manual (Page 81)

Offset Name R/W Description
9'h102 ERR_INJECT RW Bit [0] - When you write the value of 1 to this register bit,
the IP core TX MAC injects a single bit error in outgoing
Interlaken communication. This bit error will cause one or
possibly more CRC24 errors. Before you can inject a second
error, you must write the value of 0 to this register bit.
Altera recommends that you write the value of 1 and then
write the value of 0 to inject a single bit error.
If you turn off Include diagnostic features, this register is
not available.
9'h122 CNT_ERR_TX RO Number of correctable errors in M20K memory in the TX
MAC logic.
If you turn off Enable M20K ECC support, this register is
not available.
9'h123 CNT_UNCOR_TX RO Number of uncorrectable errors in M20K memory in the
TX MAC logic.
If you turn off Enable M20K ECC support, this register is
not available.
9'h124 CNT_ERR_RX RO Number of correctable errors in M20K memory in the RX
MAC logic.
If you turn off Enable M20K ECC support, this register is
not available.
9'h125 CNT_UNCOR_RX RO Number of uncorrectable errors in M20K memory in the
RX MAC logic.
If you turn off Enable M20K ECC support, this register is
not available.
Related Information
Avalon Interface Specifications
6-6 100G Interlaken IP Core Register Map
UG-01128
2015.05.04
Altera Corporation 100G Interlaken IP Core Register Map
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