Altera SerialLite II IP Core - Manual (Page 95)

Chapter 5: Testbench 5–9
Testbench Components Description
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
■ The internal counter that controls the duration of the digital resets to the ALTGX
megafunction counts up to 20 in simulation. This count overrides the default value
of 20,000.
■ The clock compensation value determines when the clock compensation sequence
is inserted into the high-speed serial stream (if Clock Compensation is enabled).
In simulation, to minimize the time it takes for the sequence to occur, the value is
always 100 cycles, independent of the actual clock compensation time value —100
or 300 parts per million (ppm).
Atlantic Receiver Behavior
The receiver (Rx) Atlantic interface signals, other than rxhpp/rxrdp_val, can be x
when the rxhpp/rxrdp_val is zero. Therefore, if the user logic uses the receive Atlantic
interface when rxhpp/rxrdp_val is zero, the receiver MegaCore function can transmit
x’s when data is not valid. This invalid data should not be used during simulation.
To ensure valid data transmission, the receive Atlantic interface should only be
sampled when the rxhpp/rxrdp_val is 1.
Testbench Components Description
This section describes the testbench components.
DUT
The Verilog HDL or VHDL IP functional simulation model of the device under test
(DUT).
SISTER
A Verilog HDL or VHDL IP functional simulation model used to test the DUT. When
the DUT is asymmetric (for example, the number of receiving lanes is different than
the number of transmitting lanes), is configured in single mode (receiver or
transmitter only), or is configured in broadcast mode, the SISTER parameters may not
match the DUT parameters, or multiple SISTER MegaCore functions may need to be
instantiated.
AGEN
This testbench includes separate versions of the AGEN module for Verilog HDL and
VHDL.
Verilog HDL
This Verilog HDL version of the AGEN module generates Atlantic data for the
SerialLite II demonstration testbench (agen_dat_dut, agen_pri_dut, agen_dat_sis,
agen_pri_sis
, and so on). The data pattern is based on an LFSR to create a predictable
but non-incrementing (pseudo-random) pattern.
This module features few tasks, the main one being the send_packet task that
transmits packets into the SerialLite II MegaCore function. It also supports the
streaming mode if the data port is configured as such.