Altera SerialLite II IP Core - Manual (Page 21)

2–6 Chapter 2: Getting Started
Parameterize
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
1 For information on setting these parameters, refer to “Flow Control” on
page 3–15 .
c. Select the transmitter and receiver buffer sizes (bytes).
18. If your transmitter or receiver requires cyclic redundancy code (CRC) checking,
turn on the Enable CRC option for your chosen packet type and specify a value
for CRC Type.
19. Click Next.
Set Up Simulation
An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model
produced by the Quartus II software. The model allows for fast functional simulation
of IP using industry-standard VHDL and Verilog HDL simulators.
c
You may use these models only for simulation and not for synthesis or any other
purposes. Using these models for synthesis creates a nonfunctional design.
To generate an IP functional simulation model for your MegaCore function, follow
these steps:
1. On the EDA page, under Simulation Libraries, turn on Generate Simulation
Model .
2. Some third-party synthesis tools can use a netlist that contains only the structure
of the MegaCore function, but not detailed logic, to optimize performance of the
design that contains the MegaCore function. If your synthesis tool supports this
feature, turn on Generate netlist.
3. Click Next to display the Summary page.
Generate Files
You can use the check boxes on the Summary page to enable or disable the generation
of specified files. A gray checkmark indicates a file that is automatically generated;
other checkmarks indicate optional files.
To generate your parameterized MegaCore function, follow these steps:
1. Turn on the files you want to generate.
2. To generate the specified files and close the SerialLite II parameter editor, click
Finish . The generation phase can take several minutes to complete.
3. If you generate the MegaCore function instance in a Quartus II project, you are
prompted to add the Quartus II IP File (.qip) to the current Quartus II project.
1
The .qip file is generated by the SerialLite II parameter editor and contains
information about a generated IP core. In most cases, the .qip file contains
all of the necessary assignments and information required to process the
MegaCore or system in the Quartus II compiler. The SerialLite II parameter
editor generates a single .qip file for each MegaCore function.