Altera SerialLite II IP Core - Manual (Page 53)

3–30 Chapter 3: Parameter Settings
Optimizing the Implementation
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
Feature Selection
The following features impact speed more significantly. Your system may require
some of these, but if any are optional or can be reconsidered, this may help your
performance. Before making any changes, verify that the feature you want to change
is in the critical speed path.
■ Lane count—running more lanes more slowly reduces the operating frequency
required (but uses more logic resources).
■ CRC—the CRC generation and checking logic degrades performance and latency.
In particular, if you are using CRC-32, evaluate carefully whether the extra
protection over CRC-16 is really worthwhile, because CRC-16 has less impact on
speed.
■ Receive FIFO buffer size—large FIFO buffers increase fanout and may require
longer routing to extend further inside the device.
Running Different Seeds
If your first attempt at hitting performance is close to the required frequency, try
running different placement seeds. This technique often yields a better result. For
information on seed specification and improving speed, you can refer to the
Command-Line Scripting and the Design Space Explorer chapters in volume 2 of the
Quartus II Handbook respectively.
Limiting Fanout
Depending on the number of lanes and the size of memories you choose, fanout can
impact performance. Limiting the fanout during synthesis causes replication of high-
fanout signals, improving speed. If high-fanout signals are the critical path, limiting
the fanout allowed can help. Refer to
volume 1 of the Quartus II Handbook for more
information on limiting fanout.
Floorplanning
The SerialLite II MegaCore function does not come with any placement constraints.
The critical paths depend on where the Fitter places SerialLite II logic in the device, as
well as the other logic in the device. You can use standard floorplanning techniques to
improve performance. Refer to
volume 2 of the Quartus II Handbook for more
information on floorplanning.
Minimizing Logic Utilization
The amount of logic required for a SerialLite II link depends heavily on the features
you choose.
The following features have a significant impact on logic usage:
■ Lane count—running fewer lanes at higher bit rates, if possible, uses less logic (but
places more of a burden on meeting performance).
■ CRC—significant savings can be made by eliminating CRC, or in particular,
moving from CRC-32 to CRC-16 in high-lane-count designs. If you are using CRC-
32, evaluate carefully whether the extra protection over CRC-16 is really
worthwhile, because CRC-16 uses far fewer resources.