Altera SerialLite II IP Core - Manual (Page 104)

5–18 Chapter 5: Testbench
Example Testbench – Verilog HDL
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
fork Launch multiple send packet loops in parallel.
begin
//////////////////////////////////////////////
// Generate RDP packets for DUT
//////////////////////////////////////////////
@(posedge trefclk);
agen_dat_dut.verbose(1);
agen_dat_dut.ipg(0,5);
amon_dat_sis.verbose(1);
fork
while (pkt_cnt_dat_dut > 0) begin : send_loop_dat_dut
integer size;
integer err;
reg [7:0] addr;
addr = $dist_uniform(seed,0,255);
size = $dist_uniform(seed,1,1024);
err = $dist_uniform(seed,0,1);
agen_dat_dut.send_packet(addr,size,err);
reset_watchdog_timer;
pkt_cnt_dat_dut = pkt_cnt_dat_dut - 1;
end
begin
fork
amon_dat_sis.wait_all_packets(packets_to_send);
join
end
join
end
Send regular data packets (on Atlantic interface) to the
DUT.
AGEN and AMON instantiations are set to display verbose
messages.
Set AGEN to insert random inner packet gaps.
Launch two processes in parallel:
- Send regular data packets to the DUT.
Define packet size, error, address.
Packet address is a random number from 0 to 255.
Packet size is a random number from 1 to 1,024.
Packet err is a random number from 0 to 1.
Call the AGEN send packet task (regular data, DUT).
Reset watchdog with every packet being sent.
Repeat this loop pkt_cnt_dat_dut times.
- Wait for the other side (Atlantic interface of the SISTER)
to receive all these packets.
Table 5–12. Example of a Demonstration Testbench (Part 2 of 5)
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