Altera SerialLite II IP Core - Manual (Page 69)

Chapter 4: Functional Description 4–15
Clocks and Data Rates
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
Figure 4–14. Receiver Layer With No FIFO
Note to Figure 4–14 :
(1) Signals are present if flow control is enabled. Drive the signal high to indicate that a flow control Link Management Packet is requested.
slite2_top
;;
;;
;;
;;
;;
high speed front
end (Phy)
slite2_ll
RX Core
rxrdp_ena
rxrdp_dav
rxrdp_sop
rxrdp_eop
rxrdp_err
rxrdp_mty
rxrdp_dat
rxrdp_adr
Atlantic
Interface
(Reg Data
Packets )
Phy Layer
Blocks (Ex
xcvr,
slite2_phy)
rxrdp_val
rxhpp_ena
rxhpp_dav
rxhpp_sop
rxhpp_eop
rxhpp_err
rxhpp_mty
rxhpp_dat
rxhpp_adr
Atlantic
Interface
(Priority
Packets )
rxhpp_val
rrefclk
tx_coreclock
err_rr_foffre_ofl
w
stat_tc_foffre_empty
stat_rr_ebprx
err_rr_bip8 err_rr_crc
err_rr_in
v
alid_lmprx
err_rr_missing_start_dc
w
err_rr_addr_mismatch
err_rr_rx2txfifo_ofl
w
stat_rr_fc_rdp_
v
alid
stat_rr_fc_hpp_
v
alid
stat_rr_fc_
v
alue
stat_rr_roe_ack
stat_rr_roe_nack
rx2tx_retimer_fifo
to TX core