Altera SerialLite II IP Core - Manual (Page 101)

Chapter 5: Testbench 5–15
Testbench Components Description
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
– PRIORITY
A value of one causes the model to receive data intended for a priority port, so that
Atlantic dav signal is ignored for all but the first transfer of a packet. A value of zero
causes the model to receive data intended for a data port, so dav is always obeyed.
defparam amon_dat_dut.PRIORITY=0;
defparam amon_pri_dut.PRIORITY=1;
– PORT_NAME
A string used to distinguish between verbose messages coming from multiple
instances of AMON.
defparam amon_dat_dut.PORT_NAME = "AMON_DAT_DUT";
defparam amon_pri_sis.PORT_NAME = "AMON_PRI_SIS";
VHDL
The VHDL version of the AMON module monitors the Atlantic data received (instances:
amon_dat_dut
, amon_dat_sis). The data received is based on a incrementing pattern.
The AMON monitor performs the following functions:
■ Validates transmission of individual packets by extracting the intended packet size
from the SOP and checking it against the actual value of the packet size counter in
the EOP.
■ Counts the total number of packets (provided as an output) to ensure that the all
packets sent are also received.
■ Checks Atlantic packets for missing SOP and EOP signals.
If any errors are detected by the AMON monitor, the error_detect output signal is
asserted.
Inner packet read gaps can optionally be enabled by driving the ipg input to the
module with a one. Doing so changes the behavior of the Atlantic read enable so that
it is instead controlled by the output of a pseudo random generator. Verbose mode for
the utility is enabled by setting the verbose integer in the generic map to one.
Status Monitors (pin_mon)
The simulation includes status pin monitors for the DUT and SISTERs
(pin_mon_). When enabled (by default), the status monitor compares the
received data against the expected data. If the expected value is different from the
current value, the monitor flags an error.
Set the en input pin high to enable a pin monitor, low to disable a pin monitor, or for
Verilog HDL only use the tasks. The Verilog HDL pin monitor expected value can be
set by a task.