Altera SerialLite II IP Core - Manual (Page 87)

January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
5. Testbench
General Description
This chapter describes the features and applications of the SerialLite II testbench to
help you successfully design and verify your design implementation.
This demonstration testbench is available in Verilog HDL for all configurations and in
VHDL for restricted configurations. The testbench shows you how to instantiate a
model in a design, it stimulates the inputs and checks the outputs of the interfaces of
the SerialLite II MegaCore function, demonstrating basic functionality.
The demonstration testbench is generic and can be used with any Verilog HDL or
VHDL simulator. The scripts allow you to run the testbench in the standard edition
(SE) or the Altera edition (AE) of the ModelSim
® software.
Figure 5–1 on page 5–3 shows the block diagram of the SerialLite II testbench. The
shaded blocks are provided with the SerialLite II testbench.
1 For Arria V and Stratix V configurations, you are required to edit the dynamically
generated testbench to include the Custom PHY IP core instantiation. For more
information about this configuration, refer to
“MegaCore Configuration for Arria V,
Cyclone V, and Stratix V Devices” on page 4–19 .
Features
The SerialLite II testbench includes the following features:
■ Easy to use simulation environment for any standard Verilog HDL or VHDL
simulator. For VHDL configurations where the VHDL demonstration testbench is
not generated, a mixed language simulator is required to simulate the Verilog
HDL testbench with the VHDL IP Functional Simulation models.
■ Open source Verilog HDL or VHDL testbench files.
■ Flexible SerialLite II functional model to verify your application that uses any
SerialLite II MegaCore function.
■ Simulates all basic SerialLite II transactions.
SerialLite II Testbench Files
The Verilog HDL demonstration testbench and associated scripts are generated when
you create a MegaCore function variation in the MegaWizard Plug-In Manager, as
described in
“Generate Files” on page 2–6 .
The VHDL demonstration testbench and the scripts to run it are generated when you
create a MegaCore function variation that meets the following criteria:
■ The language is VHDL.
■ Broadcast mode is disabled.
■ The data type is packets (streaming mode is disabled).