Altera SerialLite II IP Core - Manual (Page 106)

5–20 Chapter 5: Testbench
Example Testbench – Verilog HDL
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
begin
//////////////////////////////////////////////
// Generate HPP priority packets for DUT
//////////////////////////////////////////////
agen_pri_dut.verbose(1);
agen_pri_dut.ipg(0,5);
amon_pri_sis.verbose(1);
fork
while ( pkt_cnt_pri_dut > 0 ) begin : send_loop_pri_dut
integer size;
integer err;
reg [3:0] addr;
addr = $dist_uniform(seed,0,15);
size = $dist_uniform(seed,1,780);
err = ( $dist_uniform(seed,0,8) == 4 ) ? 1'b1 : 1'b0;
agen_pri_dut.send_packet(addr,size,err);
reset_watchdog_timer;
pkt_cnt_pri_dut = pkt_cnt_pri_dut - 1;
end
begin
fork
amon_pri_sis.wait_all_packets(packets_to_send);
join
end
join
end
Send high priority packets (on Atlantic interface) to the
DUT MegaCore function.
AGEN and AMON instantiations are set to display verbose
messages.
Set AGEN to insert random inner packet gaps.
Launch two processes in parallel:
- Send high priority packets to the DUT.
Define packet size, error, address.
Packet address is a random number from 0 to 15.
Packet size is a random number from 1 to 780.
Packet err is a random number from 0 to 1.
Call the AGEN send packet task (high priority, DUT)
Reset watchdog with every packet being sent.
Repeat this loop pkt_cnt_pri_dut times.
- Wait for the other side (Atlantic interface of the SISTER)
to receive all these packets.
Table 5–12. Example of a Demonstration Testbench (Part 4 of 5)
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