Altera SerialLite II IP Core - Manual (Page 6)

January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
1. About This MegaCore Function
SerialLite II MegaCore function is a lightweight protocol suitable for packet and
streaming data in chip-to-chip, board-to-board, and backplane applications. The
SerialLite II protocol offers low gate count and minimum data transfer latency. It
provides reliable, high-speed transfers of packets between devices over serial links.
The protocol defines packet encapsulation at the link layer and data encoding at the
physical layer, and integrates transparently with existing networks without software
support.
Release Information
Table 1–1 provides information about this release of the Altera ® SerialLite II
MegaCore ® function.
Altera verifies that the current version of the Quartus ® II software compiles the
previous version of each MegaCore function. The MegaCore IP Library Release Notes
and Errata report any exceptions to this verification. Altera does not verify
compilation with MegaCore function versions older than one release.
Device Family Support
MegaCore functions provide the following support for Altera device families:
■ Preliminary support—Altera verifies the IP core with preliminary timing models for
this device family. The core meets all functional requirements, but might still be
undergoing timing analysis for the device family. It can be used in production
designs with caution.
■ Final support—Altera verifies the IP core with final timing models for this device
family. The core meets all functional and timing requirements for the device family
and can be used in production designs.
Table 1–1. SerialLite II Release Information
Item Description
Version 13.1
Release Date November 2013
Ordering Code IP-SLITE2
Product ID 00AD
Vendor ID 6AF7