Altera SerialLite II IP Core - Manual (Page 88)

5–2 Chapter 5: Testbench
Testbench Specifications
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
■ Data packets are selected. (Priority packets are disabled.)
■ The number of Rx lanes and Tx lanes is the same.
■ The Rx buffer size is not equal to zero.
The SerialLite II testbench comprises the following files:
■ Verilog HDL or VHDL top-level testbench file: <variation_name>_tb.v or
<variation_name>_tb.vhd
■ Verilog HDL or VHDL IP functional simulation model of the device under test
(DUT): <variation_name>.vo or .vho
■ Verilog HDL or VHDL IP functional simulation model of the SISTER MegaCore
function used as a bus functional model for testing the DUT:
<variation_name>_sister_slite2_top.vo or .vho
1 All utilities are included in the testbench file: <variation_name>_tb.v or
<variation_name>_tb.vhd.
Testbench Specifications
This section describes the modules used by the SerialLite II testbench. Refer to
Figure 5–1 on page 5–3 for a block diagram of the SerialLite II testbench. The
SerialLite II testbench has the following modules:
■ Atlantic ™ generators
■ Device under test (DUT)
■ Sister device
■ Atlantic monitors
■ Clock and reset generator
■ Pin monitors
If your application requires a feature that is not supported by the SerialLite II
testbench, you can modify the source code to add the feature. You can also modify the
existing behavior to fit your application needs.
The testbench environment (tb) shown in Figure 5–1 on page 5–3 generates traffic
through the Atlantic generators (agen_dat_dut, agen_pri_dut) and sends it through
the SerialLite II MegaCore function— the device under test (DUT). The SerialLite II
interface of the DUT is connected to the SerialLite II interface of a second SerialLite II
MegaCore function—the SISTER. Data flows through the SISTER MegaCore function
and is received and checked on the Atlantic interface of the SISTER MegaCore
function (amon_dat_sis, amon_pri_sis). A similar data path exists in the opposite
direction, where the SISTER's Atlantic generators (agen_dat_sis, agen_pri_sis) send
data through the SerialLite II SISTER MegaCore function to the DUT, and data is
received on the DUT's Atlantic interface (amon_dat_dut, amon_pri_dut).
Because there is no Atlantic to Atlantic verification, the received data’s integrity is
ensured in the following ways:
■ Each Atlantic generator generates a certain number of packets or streaming bytes
which the corresponding Atlantic monitor receives.