Altera SerialLite II IP Core - Manual (Page 107)

Chapter 5: Testbench 5–21
Example Testbench – Verilog HDL
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
begin
/////////////////////////////////////////////
/
// Generate HPP priority packets for SISTER
/////////////////////////////////////////////
/
agen_pri_sis.verbose(1);
agen_pri_sis.ipg(0,5);
amon_pri_dut.verbose(1);
fork
while ( pkt_cnt_pri_sis > 0 ) begin :
send_loop_pri_sis
integer size;
integer err;
reg [3:0] addr;
addr = $dist_uniform(seed,0,15);
size = $dist_uniform(seed,1,780);
err = ( $dist_uniform(seed,0,8) == 4 ) ? 1'b1
: 1'b0;
agen_pri_sis.send_packet(addr,size,err);
reset_watchdog_timer;
pkt_cnt_pri_sis = pkt_cnt_pri_sis - 1;
end
begin
amon_pri_dut.wait_all_packets(packets_to_send
);
end
join
end
Send high priority packets (on Atlantic interface) to the
SISTER MegaCore function.
AGEN and AMON instantiations are set to display verbose
messages.
Set AGEN to insert random inner packet gaps.
Launch two processes in parallel:
- Send high priority packets to the SISTER.
Define packet size, error, address.
Packet address is a random number from 0 to 15.
Packet size is a random number from 1 to 780.
Packet err is a random number from 0 to 1.
Call the AGEN send packet task (high priority, SISTER).
Reset watchdog with every packet being sent.
Repeat this loop pkt_cnt_pri_sis times.
- Wait for the other side (Atlantic interface of the DUT) to
receive all these packets.
join All loops must finish (receive all packets) before
exiting.
tc_end(`TBID);
exit;
end
End of test case.
Main initial block end.
endmodule End of testbench main section.
//SERIALLITE2_TB_MAIN_END
Table 5–12. Example of a Demonstration Testbench (Part 5 of 5)
Main Section Comments