Altera SerialLite II IP Core - Manual (Page 80)

4–26 Chapter 4: Functional Description
Signals
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
rxrdp_eop (1) Output rxrdp_clk End of packet indicator on the Atlantic interface.
rxrdp_err (1) Output rxrdp_clk
Error indicator on the Atlantic Interface. This signal is
not necessarily held high until rxrdp_eop is
asserted.
rxrdp_mty[ m-1:0]
(1) , (2)
Output rxrdp_clk Number of empty bytes in the data word.
rxrdp_dat[ d-1:0]
(1) , (3)
Output rxrdp_clk User data bits.
rxrdp_adr[7:0] (1) Output rxrdp_clk User-defined packet ID. Only valid with rxrdp_sop.
txrdp_ena Input txrdp_clk
Enable signal on the Atlantic interface. Indicates that
the data is valid.
txrdp_dav Output txrdp_clk Indicates that the input FIFO buffer is not full.
txrdp_sop Input txrdp_clk Start of packet indicator on the Atlantic interface.
txrdp_eop Input txrdp_clk End of packet indicator on the Atlantic interface.
txrdp_err Input txrdp_clk Error indicator on the Atlantic interface.
txrdp_mty[ tm-1:0] (4) Input txrdp_clk Number of empty bytes in the data word.
txrdp_dat[ td-1:0] (5) Input txrdp_clk User data bits.
txrdp_adr[7:0] Input txrdp_clk User-defined packet ID.
rxhpp_ena (1) Input rxhpp_clk
Enable signal on the Atlantic interface. Indicates that
the data is to be read on the next clock cycle.
rxhpp_dav (1) Input rxhpp_clk
Input (No FIFO buffer) determines whether flow
control is required on this port.When this signal is
low, the fill level has been breached. When this signal
is high, the FIFO buffer has enough space for more
words.
rxhpp_dav (1) Output rxhpp_clk
Output (With FIFO buffer) represents the buffer’s fill
level. This signal is high when the level is above FTL
or if an EOP is in the buffer.
rxhpp_val (1) Output rxhpp_clk The output data is valid.
rxhpp_sop (1) Output rxhpp_clk Start of packet indicator on the Atlantic interface.
rxhpp_eop (1) Output rxhpp_clk End of packet indicator on the Atlantic interface.
rxhpp_err (1) Output rxhpp_clk
Error indicator on the Atlantic Interface. This signal is
not necessarily held high until rxhpp_eop is
asserted.
rxhpp_mty[ m-1:0]
(1) , (2)
Output rxhpp_clk Number of empty bytes in the data word.
rxhpp_dat[ d-1:0]
(1) , (3)
Output rxhpp_clk User data bits.
rxhpp_adr[3:0] (1) Output rxhpp_clk User-defined packet ID. Only valid with rxhpp_sop.
txhpp_ena Input txhpp_clk
Enable signal on the Atlantic interface. Indicates that
the data is valid.
txhpp_dav Output txhpp_clk Indicates that the input FIFO buffer is not full.
txhpp_sop Input txhpp_clk Start of packet indicator on the Atlantic interface.
txhpp_eop Input txhpp_clk End of packet indicator on the Atlantic interface.
Table 4–7. Atlantic Interface Signals (Part 2 of 3)
Signal Direction Clock Domain Description