Altera SerialLite II IP Core - Manual (Page 23)

2–8 Chapter 2: Getting Started
Compile and Program
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
Fitter Constraints
The Tcl script also optimizes fitter settings to produce the best performance (f
MAX
).
Use this script as a guide to set constraints for the SerialLite II MegaCore function
variation in your design. The timing constraints are currently set for the SerialLite II
MegaCore function variation as a standalone component, thus you must update the
script with hierarchy information for your own design. The Tcl script also points to
the generated Synopsys Design Constraints (SDC) timing constraint script if the
TimeQuest timing analyzer is enabled. The Fitter optimizes your design based on the
requirements in the .sdc files in your project.
The script uses the FITTER_EFFORT "STANDARD FIT" Fitter setting.
1 This fitter setting may conflict with your Quartus II software settings.
You can now integrate your MegaCore function variation into your design and
simulate and compile.
Timing Constraints
The SerialLite II MegaCore generates an ASCII file (with the .sdc extension) that
contains design constraints and timing assignments in the industry-standard SDC
format. The constraints in the .sdc file are described using the Tcl tool command
language and follow Tcl syntax rules.
To specify the TimeQuest timing analyzer as the default timing analyzer, on the
Assignments menu, click Timing Analysis Settings. In the Timing Analysis Settings
page, turn on Use TimeQuest Timing Analyzer during compilation.
The TimeQuest timing constraints are currently set for the SerialLite II MegaCore
function variation as a standalone component. You must update the script with
hierarchy information if your own design is not a standalone component.
f
Refer to the Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II
Handbook for more information on how to use the TimeQuest Timing Analyzer.
Compile and Program
Click Start Compilation on the Processing menu in the Quartus II software to compile
your design. After successfully compiling your design, program the targeted Altera
device with the Programmer (Tools menu) and verify the design in hardware.