Altera SerialLite II IP Core - Manual (Page 18)

Chapter 2: Getting Started 2–3
Parameterize
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
3. Under Installed Plug-Ins, expand Interfaces folder and then, click
SerialLite II .
4. Select the output file type for your design; the MegaWizard Plug-In Manager
supports VHDL and Verilog HDL. For this example, select Verilog HDL.
5. The MegaWizard Plug-In Manager shows the project path that you specified in the
New Project Wizard . Append a variation name for the MegaCore function output
files <project path>\<variation name>. For this example, type example as the
variation name.
6. Click Next to display the Parameter Settings page for the SerialLite II MegaCore
function.
Parameterize
This section shows how to parameterize the example SerialLite II MegaCore function
and describes the results of various options. A comprehensive description of all
parameters is contained in
Chapter 3, Parameter Settings .
1 The following parameters are ordered as they appear in the SerialLite II parameter
editor. Not all parameters are supported by, or are relevant for, every MegaCore
function variation.
To parameterize your MegaCore function, follow these steps:
1. Click Parameter Settings in the SerialLite II parameter editor. The Physical Layer
page appears.
2. Enter a data rate in megabits per second (Mbps). The SerialLite II MegaCore
function supports data rates of 622 to 6,375 Mbps per lane.
The data rate must be an acceptable range for the Transfer size. SerialLite II
returns a warning or an error message if you specify a data rate that is not within
the range for the specified Transfer size.
3. Choose a Transfer size. The Transfer size determines the number of contiguous
data columns. The Transfer size also determines the serialization/deserialization
(SERDES) factor and internal data path width:
■ A Transfer size of 1 equates to an internal data path of 8 bits (Recommended
for less than 2.5 gigabits per second (Gbps))
■ A Transfer size of 2 equates to an internal data path of 16 bits (Recommended
for less than or equal to 3.125 Gbps)
■ A Transfer size of 4 equates to an internal data path of 32 bits (Typically for
greater than 3.125 Gbps, and only available for Stratix IV devices)
4. Specify the Reference Clock Frequency. This option defines the frequency of the
reference clock for the Arria II GX or Stratix IV internal transceiver. You can select
any frequency supported by the transceiver. This option is not available in Arria V,
Cyclone V, and Stratix V configurations.
5. Select a Port Type. You have three choices: Bidirectional, Transmitter only, and
Receiver only .