Altera SerialLite II IP Core - Manual (Page 31)

3–8 Chapter 3: Parameter Settings
Physical Layer Configuration
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
2. Wait for the rx_freqlocked signal (stat_rr_freqlock) to be asserted, which
happens when the ALTGX megafunction locks onto the serial stream; 5 ms or less
is normal.
3. The Rx digital reset needs to complete; this reset normally takes one million
internal tx_coreclock cycles after rx_freqlocked is asserted. The
stat_tc_rst_done
signal is asserted to indicate that the reset sequence has been
completed.
1 The normal time values are much shorter in simulation (For example, using
the IP Functional Simulation Model), but not in gate-level simulation. Gate-
level simulation uses the hardware equivalent times.
As you have full visibility of the above signals (via the SignalTap ® II logic analyzer
and the port list), you should characterize the timing of these signals to set up the size
of your ctrl_tc_force_train counter. The MegaCore function also has a reset done
status signal (stat_tc_rst_done) that can be useful for measurements. The following
MegaCore function status output signals correspond to each step above:
■ stat_tc_pll_locked
■ stat_rr_freqlock
■ stat_tc_rst_done (to see when rx_digitalreset has been negated).
After the reset controller completes, the MegaCore function waits for the transceiver
byte aligner to detect and align the control (k28.5) character in the training sequence.
Once the transceiver detects this character, the count starts at every k28.5 that is
received (basically, counting every training sequence). Once 64 error-free training
sequences have been received, the MegaCore function reports linkup. Any errors (for
example, disparity or 8B/10B errors) that are received reset the count, and the
MegaCore function continues to wait until 64 error-free training patterns are received.
1 The self-synchronizing LSM also locks onto the clock compensation sequence. As
turning on the Clock Compensation option allows the receiver to automatically
relock if the link goes down, the transmitter is not required to assert
ctrl_tc_force_train
to retrain the link (which may be impossible in a unidirectional
link because the transmitter does not necessarily detect that the receiver has lost the
link).
Number of Lanes
Because each lane operates at the bit rate, you can increase the bandwidth by adding
lanes. Adding lanes—up to a maximum of 16—is a simple way to scale the link
during system design. If adding a lane provides more bandwidth than needed, you
can reduce the system clock rate, thereby mitigating possible high-speed design issues
and making it easier to meet performance.