Cirrus Logic CS42L56 - Manual (Page 9)

DS851F2 9
CS42L56
-VHPFILT 11
Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge
pump that provides the negative rail for the headphone and line amplifiers.
HPOUTA
HPOUTB 12
14 Headphone Audio Output (Output) - The full-scale output level is specified in “HP Output Charac-
teristics” on page 19 .
HPREF 13
Pseudo Diff. Headphone Output Reference (Input) - Ground reference for the headphone amplifi-
ers
TSTN
15
16 Test Input (Input) - This pin is an input used for test purposes only and should be tied to ground for
normal operation.
LINEOUTA
LINEOUTB 17
19 Line Audio Output (Output) - The full-scale output level is specified in “Line Output Characteristics”
on page 20 .
LINEREF 18 Pseudo Diff. Line Output Reference (Input) - Ground reference for the line amplifiers.
VA 20 Analog Power (Input) - Power supply for the internal analog section.
AGND 21 Analog Ground (Input) - Ground reference for the internal analog section.
FILT+ 22 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
VQ 23 Quiescent Voltage (Output) - Filter connection for the internal quiescent voltage.
AFILTA
AFILTB 24
25
Antialias Filter Connection (Output) - Antialias filter connection for the ADC inputs.
MICBIAS
26 Microphone Bias (Output) - Low noise bias supply for an external microphone. Electrical character-
istics are specified in the DC Electrical Characteristics table.
AIN1A
AIN1B
AIN2A
AIN2B 27
29
30
32
Analog Inputs 1 & 2 (Input) - The full-scale level is specified in “Analog Input Characteristics” on
page 14 .
AIN1REF/AIN3A
AIN2REF/AIN3B 28
31
Pseudo Differential Analog Input Reference/Analog Input 3 (Input) - Configurable as the ground
reference for the programmable gain amplifiers (PGA) or as additional analog inputs. The full-scale
level is specified in
“Analog Input Characteristics” on page 14 .
HPDETECT 33
Headphone Detect (Input) - The HPDETECT circuit can be set to control the power down of the left
and/or right channel of the line and/or headphone outputs as described in
“Headphone Power Con-
trol” on page 59 and “Line Power Control” on page 60 and/or cause an interrupt. This pin is
debounced such that the signal must remain stable in the new state for approximately 10 ms before
a change is passed on to the internal HPDETECT circuit.
RESET 34 Reset (Input) - The device enters a low power mode when this pin is driven low.
VLDO 35 Low Dropout Regulator (LDO) Power (Input) - Power supply for the LDO regulator.
VDFILT 36
Low Dropout Regulator (LDO) Filter Connection (Output) - Power supply from the LDO regulator
that provides the low voltage power to the digital section.
VL 37
Digital Interface Power (Input) - Determines the required signal level for the serial audio interface
and I²C control port.
SDOUT 38 Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
MCLK 39 Master Clock (Input) - Clock source for the delta-sigma modulators.
SCLK 40 Serial Clock (Input/Output) - Serial clock for the serial audio interface.
GND/
Thermal Pad
- Ground reference for the internal charge pump and digital section; thermal relief pad.