Cirrus Logic CS42L56 - Manual (Page 61)

DS851F2 61
CS42L56
6.6.2 Clock Ratio
Configures the appropriate internal MCLK divide ratio for LRCK and SCLK.
Notes:
1. Register settings not shown in the table are reserved. Use
Table 3. “Serial Port Clock Ratio Settings”
beginning on page 47 for determining the register settings based on the system master clock (MCLK),
bit clock (SCLK) and frame clock (LRCK) frequencies.
6.7 Serial Format (Address 07h)
6.7.1 CODEC Digital Interface Format
Configures the digital interface format for data on SDOUT and SDIN.
RATIO[4:0] MCLK/LRCK Ratio MCLK/SCLK Ratio
01000 128 2
01001 125 2
01011 136 2
01100 192 3
01101 187.5 3
10000 256 4
10001 250 4
10011 272 4
10100 384 6
10101 375 6
11000 512 8
11001 500 8
11011 544 8
11100 750 12
11101 768 12
Application: “Serial Port Clocking” on page 47
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved DIF Reserved Reserved Reserved
DIF CODEC Interface Format
0 I²S
1 Left Justified
Application: