Cirrus Logic CS42L56 - Manual (Page 31)

DS851F2 31
CS42L56
4.2 Analog Inputs
Referenced Control Register Location
Analog Front End
AIN1x_REF
AIN2x_REF
PREAMPx[1:0]
PGAxMUX[1:0]
PDN_ADCx
PGAxVOL[5:0]
PGAB=A
ANLGZCx
ADCxMUX[1:0]
INV_ADCx
PDN_CHRG
HPFRZx
HPFx
HPFx_CF[1:0]
Digital Volume
BOOSTx
ADCxMUTE
ADCxATT[7:0]
DIGSFT
ADCB=A
ALCx
ALCxSRDIS
ALCxZCDIS
ALCARATE[5:0]
ALCRRATE[5:0]
MAX[2:0]
MIN[2:0]
NGALL
NG
THRESH[3:0]
NGDELAY[1:0]
Miscellaneous
DIGSUM[1:0]
DIGMUX
“Analog Input 1 x Reference Configuration” on page 74
“Analog Input 2 x Reference Configuration” on page 74
“PGA x Preamplifier Gain” on page 77
“PGA x Input Select” on page 77
“Power Down ADC x” on page 59
“PGAx Volume” on page 78
“PGA Channel B=A” on page 76
“Analog Zero Cross” on page 64
“ADC x Input Select” on page 75
“Invert ADC Signal Polarity” on page 76
“Power Down ADC Charge Pump” on page 59
“ADCx High-Pass Filter Freeze” on page 75
“ADCx High-Pass Filter” on page 75
“HPF x Corner Frequency” on page 75
“Boostx” on page 77
“ADC Mute” on page 76
“ADCx Volume” on page 78
“Digital Soft Ramp” on page 64
“ADC Channel B=A” on page 76
“ALCx” on page 79
“ALCx Soft Ramp Disable” on page 82
“ALCx Zero Cross Disable” on page 82
“ALC Attack Rate” on page 79
“ALC Release Rate” on page 80
“ALC Maximum Threshold” on page 80
“ALC Minimum Threshold” on page 81
“Noise Gate All Channels” on page 81
“Noise Gate Enable” on page 81
“Noise Gate Threshold and Boost” on page 82
“Noise Gate Delay Timing” on page 82
“Digital Sum” on page 76
“Digital MUX” on page 63
`
Gain Adjust
ALC
PDN_ADCA
PGAAVOL[5:0]
PGAB=A
ANLGZC
HPFRZA
HPFA
HPFA_CF[1:0] PDN_ADCA
INV_ADCA
PDN_CHRG
ALCB
ALCBSRDIS
ALCBZCDIS
PC
M
Ser
ial
In
te
rfa
ce
TO DSP Engine
ALCARATE[5:0]
ALCRRATE[5:0]
ALCMAX[2:0]
ALCMIN[2:0]
ALCA
ALCASRDIS
ALCAZCDIS
AIN1A
AIN2A
ADC
PDN_ADCB
PGABVOL[5:0]
PGAB=A
ANLGZC
BOOSTB
ADCBMUTE
DIGSFT
ADCBATT[7:0]
ADCB=A
HPFRZB
HPB
HPFB_CF[1:0] PDN_ADCB
INV_ADCB
PDN_CHRG
Noise Gate
NGALL
NG
THRESH[3:0]
NGDELAY[1:0]
Gain Adjust
FROM DSP ENGINE
DIGMUX
ANALOG PASSTHRU TO
HEADPHONE, LINE AMPLIFIER MUX
Swap/
Mix
DIGSUM[1:0]
BOOSTA
ADCAMUTE
DIGSFT
ADCAATT[7:0]
ADCB=A
ADC
ADCAMUX[1:0]
AIN2REF
/ AIN3B
PGAAMUX[1:0]
PREAMPA[1:0]
AIN1B
AIN2B
ADCBMUX[1:0]
AIN1REF
/ AIN3A
AIN1A_REF
AIN2A_REF
PGA A
PGABMUX[1:0]
PREAMPB[1:0]
AIN1B_REF
AIN2B_REF
PGA B
VQ
Figure 13. Analog Input Signal Flow