Cirrus Logic CS42L56 - Manual (Page 59)

DS851F2 59
CS42L56
6.4.2 Line Power Control
Configures how the HPDETECT pin, 29, controls the power for the line amplifier.
6.5 Clocking Control 1 (Address 05h)
6.5.1 Master/Slave Mode
Configures the serial port I/O clocking.
6.5.2 SCLK Polarity
Configures the polarity of the SCLK signal.
6.5.3 SCLK Equals MCLK
Configures the SCLK signal source and speed for master mode.
Note: The SCK=MCK[1:0] bits must be set to “00” when the device is in slave mode.
6.5.4 MCLK Pre-Divide
Configures a divide of the input MCLK prior to all internal circuitry.
PDN_LINx[1:0] Line Status
00
Line channel is ON when the HPDETECT pin, is LO.
Line channel is OFF when the HPDETECT pin, is HI.
01
Line channel is ON when the HPDETECT pin, is HI.
Line channel is OFF when the HPDETECT pin, is LO.
10 Line channel is always ON.
11 Line channel is always OFF.
7 6 5 4 3 2 1 0
Reserved M/S INV_SCLK SCK=MCK1 SCK=MCK0 MKPREDIV MCLKDIV2 MCLKDIS
M/S Serial Port Clocks
0 Slave (Input ONLY)
1 Master (Output ONLY)
Application: “Serial Port Clocking” on page 47
INV_SCLK SCLK Polarity
0 Not Inverted
1 Inverted
SCK=MCK[1:0] Output SCLK
00 Re-timed, bursted signal with minimal speed needed to clock the required data samples
01 Reserved
10 MCLK signal after the MCLK divide by 2 (MCLKDIV2) circuit
11 MCLK signal before the MCLK divide by 2 (MCLKDIV2) circuit
MKPREDIV MCLK signal into CODEC
0 No divide
1 Divided by 2
Application: “Serial Port Clocking” on page 47